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ADE7518
Table 114. Alarm Interval SFR (INTVAL, 0xA6)
Bit
7 to 0
Mnemonic
INTVAL
Default
0
Description
The interval timer counts according to the time base established in the ITS[1:0] bits of the RTC Configuration
SFR (TIMECON, 0xA1). Once the number of counts is equal to INTVAL, the ALARM flag is set and a
pending RTC interrupt is created. Note that the interval counter is eight bits. Therefore, it can count up to
255 seconds, for example.
Table 115. RTC Nominal Compensation SFR (RTCCOMP, 0xF6)
Bit
7 to 0
Mnemonic
RTCCOMP
Default
0
Description
The RTCCOMP SFR holds the nominal RTC compensation value at 25°C. This register is retained during
a watchdog reset or an external reset. It is reset after a POR.
Table 116. RTC Temperature Compensation SFR (TEMPCAL, 0xF7)
Bit
7 to 0
Mnemonic
TEMPCAL
Default
0
Description
The TEMPCAL SFR is adjusted based on a temperature read. This allows the external crystal shift to be
compensated over temperature. This register is retained during a watchdog reset or an external reset.
It is reset after a POR.
Table 117. Interrupt Pins Configuration SFR (INTPR, 0xFF)
Bit
7
Mnemonic
RTCCAL
Default
0
Description
Controls the RTC calibration output. When set, the RTC calibration frequency selected by FSEL[1:0] is
output on the P0.2/CF1/RTCCAL pin.
6 to 5
4
3 to 1
0
FSEL[1:0]
Reserved
INT1PRG[2:0]
INT0PRG
00
0
000
0
Sets RTC calibration output frequency and calibration window.
FSEL[1:0]
Result (Calibration Window, Frequency)
00
30.5 sec, 1 Hz
01
30.5 sec, 512 Hz
10
0.244 sec, 500 Hz
11
0.244 sec, 16.384 kHz
This bit must be set to 0 for proper operation.
Controls the function of INT1.
INT1PRG[2:0]
Result
x00
GPIO
x01
BCTRL
01x
INT1 input disabled
11x
INT1 input enabled
Controls the function of INT0.
INT0PRG
Result
0
INT0 input disabled
1
INT0 input enabled
Table 118. Key SFR (KYREG, 0xC1)
Bit
7 to 0
Mnemonic
KYREG
Default
0
Description
Write 0xA7 to this SFR before writing to the POWCON SFR, which unlocks KYREG.
Write 0xEA to this SFR before writing to the INTPR, HTHSEC, SEC, MIN, or HOUR timekeeping registers
to unlock KYREG.
Rev. 0 | Page 102 of 128
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